The present invention relates to charge pump circuits used in a Phase Locked Loop (PLL), and in particular to techniques for reducing the capacitor size of the loop filter capacitor.
A conventional differential charge pump circuit with a loop filter included is shown in FIG. 1. Typically, the input to the charge pump circuit is the phase difference between a received signal and a signal attempting to lock-on to the receive signal. The output of the charge pump would typically be provided to a voltage controlled oscillator (VCO) to adjust the oscillator frequency accordingly to match the phase of the input signal. The low pass loop filter is coupled to the output of the charge pump to provide an analog output control voltage to the VCO.
As shown in FIG. 1A, a pump up signal from the phase detector is provided on an input 10, and a pump down signal on an input 12. These low-active signals switch on switching transistors M1 and M3, respectively. The current to M1 and M3 is provided by current source transistors 14 and 16, which each provides a current I.
When the pump down signal is applied on line 12, current I flows through turned on transistor M3, through resistor RN, capacitor Cloop resistor RP, and through transistor M5. The positive version of a pump down signal (pdn) will turn on an MOS transistor M5, providing a sink path for the current. At the same time, the pump up signal will be off, turning off transistor M1 and corresponding transistor M7. Transistors 13 and 15 are current sink transistors.
When the pump down signal is inactive, and the pump up signal is active, and transistors M1 and M7 will be on, providing current I in the opposite direction through the capacitor. Transistors 17, 18, 20 and 22 are provided to give a path to steer the current away from the loop filter when their corresponding switching transistors M3, M1, M5 and M7 are turned off. Amplifier 24 is a Common Mode Feed Back (CMFB) amplifier.
Typically, the capacitor is a discrete capacitor which is off-chip. This is because the capacitor needs to be large enough to satisfy design requirements. For example, for SONET, there is a 0.1 dB peaking limit, which requires a large capacitor. This cannot be achieved by simply using a smaller current and smaller capacitor, since that would adversely impact other design requirements.
FIG. 1B illustrates, in a simplified manner, the loop filter composed of resistors RN, RP and capacitor Cloop in FIG. 1A. The shunt capacitors to ground CS, for the lead-lag filter are also included.
One approach to provide an on-chip capacitor which is smaller, and thus doesn""t require a large silicon area, is illustrated in U.S. Pat. No. 6,344,772, inventor Patrik Larsson. This patent shows an operational amplifier based capacitor multiplication circuit. In essence, through the use of an operational amplifier the effective capacitance value can be multiplied. Unfortunately, this introduces problems of its own, such as problems with Power Supply Rejection Ratio (PSRR), offset, bandwidth and noise. However, it does avoid the problems associated with off-chip capacitors, such as leakage and parasitic capacitance.
FIG. 2 illustrates in simplified format the operational amplified-based circuit, using an operational amplifier 30 with resistors R1 and R2, and capacitor C. The right side of FIG. 2 shows the equivalent circuit with the effective resistance, Reff and the effective capacitance, Ceff. The below analysis demonstrates how this capacitor multiplication effect is achieved.
Since                                           V            x                    =                                    1                              1                +                                  sCR                  1                                                      ⁢                          xe2x80x83                        ⁢                          V              o                                      ,                            (        a        )                                          I          1                =                                                                              V                  o                                -                                  V                  x                                                            R                1                                      ⁢                          xe2x80x83                        ⁢            and            ⁢                          xe2x80x83                        ⁢                          I              2                                =                                                                      V                  o                                -                                  V                  x                                                            R                2                                      ⁢                          xe2x80x83                        ⁢            and                                              (        b        )                                                      V            o                    -                      V            x                          =                                            sCR              1                                      1              +                              sCR                1                                              ⁢                      xe2x80x83                    ⁢                      V            o                                              (        c        )            
Now                                                         Z              =                              xe2x80x83                            ⁢                                                V                  o                                                                      I                    1                                    +                                      I                    2                                                                                                                                          =                                  xe2x80x83                                ⁢                                                                            R                      1                                        ⁢                                          xe2x80x83                                        ⁢                                          R                      2                                        ⁢                                          xe2x80x83                                        ⁢                                          V                      o                                                                                                  (                                                                        R                          1                                                +                                                  R                          2                                                                    )                                        ⁢                                          xe2x80x83                                        ⁢                                          (                                                                        V                          o                                                -                                                  V                          x                                                                    )                                                                                  ,                                                                          =                              xe2x80x83                            ⁢                                                                                          R                      1                                        ⁢                                          xe2x80x83                                        ⁢                                          R                      2                                                                                                  R                      1                                        +                                          R                      2                                                                      ⁢                                  xe2x80x83                                ⁢                                  (                                      1                    +                                          1                                              sCR                        1                                                                              )                                                                                                        =                              xe2x80x83                            ⁢                                                                                          R                      1                                        ⁢                                          xe2x80x83                                        ⁢                                          R                      2                                                                                                  R                      1                                        +                                          R                      2                                                                      +                                  1                                      sC                    ⁢                                          xe2x80x83                                        ⁢                                          (                                              1                        +                                                                              R                            1                                                                                R                            2                                                                                              )                                                                                                                                                              ≈                                  xe2x80x83                                ⁢                                                                                                    R                        1                                            ⁢                                              xe2x80x83                                            ⁢                                              R                        2                                                                                                            R                        1                                            +                                              R                        2                                                                              +                                      1                                          sC                      ⁢                                              xe2x80x83                                            ⁢                                                                        R                          1                                                                          R                          2                                                                                                                                ,                                                                    if                    ⁢                                          xe2x80x83                                        ⁢                                                                  R                        1                                                                    R                        2                                                                              =                  K                                 greater than  greater than                 1                                                                                        =                              xe2x80x83                            ⁢                                                R                  1                                //                                                      R                    2                                    +                                      1                                          sC                      eff                                                                                                                              from        ⁢                  xe2x80x83                ⁢                  Eqs          .                      xe2x80x83                    ⁢                      (            a            )                          ⁢                  –                ⁢                  (          c          )                    
where
Ceff≈KC
The present invention provides a charge pump circuit with a small loop filter capacitor. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the multiple currents through the resistors. In this way, a smaller current is provided through the capacitor, allowing the capacitor to be much smaller in size.
In one embodiment, two switching transistors are provided in parallel for each of the pump up and pump down inputs, with the size of the transistor providing the appropriate fractional current. One switching transistor provides the current I through the resistor, but a separate switching transistor diverts a fractional part of it so that it does not flow through the capacitor. A third switching transistor provides current through a second transistor in a differential design, bypassing the capacitor, such that the combined current from the current portion passing through the capacitor and the current portion separately provided to the additional resistor combine to make the total current I.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description in conjunction with the accompanying drawings.